1. Field of the Invention
The present invention provides a pixel structure and a manufacture method for use in a liquid crystal display (LCD), specifically, in a fringe field switching LCD (FFS-LCD).
2. Descriptions of the Related Art
Among all kinds of display products currently available, the liquid crystal display (LCD) is becoming the mainstream product. However, there are still some image display problems in LCDs, such as slow response speed and low aperture ratios. To overcome such problems, a fringe field switching LCD (FFS-LCD) has been proposed, which, compared to the conventional in-plane switching LCD (IPS-LCD), has an improved aperture ratio, a better overall light transmittance, and also a higher response speed.
In the pixel structure of the FFS-LCD, the pixel electrode and common electrode are stacked with and insulated from each other in the display area. In particular, the pixel electrode contains a slit structure so that when a voltage is applied to the pixel electrode and the common electrode, an electric field is generated between the fringe of the slit structure of the pixel electrode and the common electrode to control the twisting of the liquid crystal molecules in the pixel structure.
The pixel structure of a conventional FFS-LCD is depicted in FIG. 1A and FIG. 1B, and a manufacturing method thereof is depicted in FIG. 1C to FIG. 1I. The pixel structure comprises a control area 111 and a display area 112. For convenience, FIGS. 1B to 1I are depicted as cross-sectional views taken along lines A-A′, B-B′ and C-C′ in FIG. 1A. In manufacturing the pixel structure of a conventional FFS-LCD, a patterned first metallic layer 120 is initially formed on the substrate 110 by a photolithography-etching process. As shown in FIG. 1C, the patterned first metallic layer 120 comprises a gate electrode 121 and a gate line 123, in which the gate line 123 is extended to the pad area 113 of the substrate 110.
Subsequently, the first insulating layer 130 is formed to overlay the first metallic layer 120. Then, a patterned semi-conductive layer 140 is formed on the first insulating layer 130 corresponding to the gate electrode 121 by a second photolithography-etching process, as shown in FIG. 1D. The semi-conductive layer 140 may comprise a semi-conductive channel layer and an ohmic contact layer (not shown).
Next, a first contact hole 131 is formed on the first insulating layer 130 by a third photolithography-etching process to partially expose the gate line 123 in the pad area 113, as shown in FIG. 1E. Following this, a patterned second metallic layer 150 is formed by a fourth photolithography-etching process. The second metallic layer 150 comprises a source electrode 151, a drain electrode 152, a data line 153 and a first gate line pad layer 154, which are formed simultaneously. The source electrode 151 and the drain electrode 152 are electrically connected to the semi-conductive layer 140 respectively. The data line 153 is configured to receive a signal for controlling the pixel structure. The first gate line pad layer 154 is electrically connected to the gate line 123 via the first contact hole 131, as shown in FIG. 1F.
Thereafter, a second insulating layer 160 is formed to overlay the aforesaid structure. Then, a patterned transparent electrode layer is formed on the second insulating layer 160 by a fifth photolithography-etching process to form a common electrode 171, as shown in FIG. 1G
Then, a third insulating layer 180 is formed, and the third insulating layer 180 and the second insulating layer 160 are patterned by a sixth photolithography-etching process. As a result, a second contact hole 181 is etched, partially exposing the drain electrode 152. Likewise, a third contact hole 182 is etched as well, partially exposing the first gate line pad layer 154, as shown in FIG. 1H. Next, a seventh photolithography-etching process is performed to form a patterned third metallic layer 190, which comprises a pixel electrode 191 and a second gate line pad layer 192. The pixel electrode 191 is formed on the display area 112 and is electrically connected to the drain electrode 152 via the second contact hole 181, while the second gate line pad layer 192 is electrically connected to the first gate line pad layer 154 via the third contact hole 182. Thereby, the second gate line pad layer 192 is electrically connected to the gate line 123 electrically, as shown in FIG. 1I.
In summary, in manufacturing the pixel structure of a conventional FFS-LCD, at least seven photolithography-etching processes are needed. The pixel structure formed comprises three insulating layers to give rise to high manufacturing costs and long manufacturing times. Accordingly, it is highly desirable to reduce the number of photolithography-etching processes and insulating layers required, while still maintaining the aperture ratio of the pixel structure.